Recently, with the progress of semiconductor manufacturing techniques and with the expansion of the application of semiconductor memory devices of large capacities are developed and promoted. Particularly, large capacity ROMs which are simple in structure and which do not require fastidious manufacturing processes are being rapidly developed.
To increase memory cell density, various manufacturing methods for mask ROM such as contact mask method, diffused layer mask method, NAND type ion-implantation method, and multi-gate method have been proposed and put to practical uses, the methods being selectively adopted depending on the memory cell structure.
The multi-gate type ROM (hereinafter "MUGROM") has a multi-gate MOS transistor structure which is similar to the structure of the charge coupled device (CCD), and consists of memory cell arrays. (Refer to "4 mega bit full wafer ROM," 1980 IEEE international solid state circuit conference, pp 150-151).
FIG. 1 illustrates a plan view of a MUGROM cell array structure, and FIG. 2 illustrates a transistor equivalent circuit for the MUGROM cell array of FIG. 1. A MUGROM cell array has a plurality of gate electrodes which are formed by a double polycrystalline silicon gate process on the channel region located between a drain region 1 and a source region 2. A bit line B is connected through a metallic contact hole 3 to drain region 1. The source region 2 serves as a common source line CS; the gate electrodes serve as word lines W. FIG. 3 is a cross-sectional view taken along the line A--A of FIG. 1. The areas C drawn in oblique lines in FIG. 1 indicate the channel regions where an impurity of an opposite type to that of the substrate is doped. That is, if the substrate is doped with a P type impurity, the channel regions are doped with an N type impurity. Accordingly, the ion-implanted regions will constitute channel depletion type transistors (M1, M3, and M6 in FIG. 2), while the remaining regions constitute channel enhancement type transistors (M2, M4 and M5 in FIG. 2).
The channel depletion type transistors and channel enhancement type transistors have different gate threshold voltages respectively represented by information level "1" and "0". The manufacturing process for such a MUGROM will be described referring to FIG. 4.
FIG. 4a illustrates a doping process in which first a field oxide layer is grown to define an active region, and an N type impurity such as arsenic is ion-implanted into a predetermined first channel region 20a. The ion-implantation is by applying a first cell ion-implanting mask 11 on a P type silicon substrate. The substrate is one which has undergone a P type impurity-doping process for adjusting the threshold voltage on the active region.
FIG. 4b illustrates an ion implanting process in which first a first gate oxide film 12 is grown and a first polycrystalline silicon layer is deposited after the completion of the first cell ion implanting process. Then, first gate electrodes 13 are formed through an etching process for the first polycrystalline silicon layer by applying a first gate mask. Then, an N type impurity is ion-implanted into a predetermined second channel region 20b by applying a second cell ion implanting mask 14.
FIG. 4c illustrates a process in which the photoresist, i.e., the second cell ion implanting mask 14 is removed after the completion of the second cell ion implanting process. Then, a second gate oxide film 15 is grown on it, and then a second polycrystalline silicon layer is deposited on it. Then, second gate electrodes 16 are formed through an etching process directed to the second polycrystalline silicon layer by applying a second gate mask.
FIG. 4d illustrates a state after the completion of a process in which first and second insulating layers 17, 18 are successively formed on the above mentioned first and second gate electrodes 13, 16, and after a metallization process is carried out.
In the above described conventional MUGROM manufacturing method, the first polycrystalline silicon gate electrode layer 13c is liable to be mis-aligned on the first cell ion-implanted region 20a, because the first polycrystalline silicon gate electrode layer 13c is formed after the completion of the first cell ion-implanting process.
Accordingly, due to the mis-alignment problem, the cell ion-implanting mask has to be made larger than that which is necessary for the actual cell channel region. That constitutes a limitation in an effort to reduce the length of the channel. Moreover, where the mis-alignment problem is severe, the bit line is rendered inoperational, resulting in a lower production yield.
Also, as the density of cells increase, the area of cells diminish; the tolerance for mis-alignment is proportional to the area of cells. When cell areas have to be made larger than that otherwise necessarily required, as described above, a limitation is imposed on the increases in cell density, and large capacity ROMs cannot be achieved.